Logic designers of so-called “System-on-a-Chip” and similar products have a broad range of components to select from. For example, the designer can use high performance logic gates, latches, static random access memory (SRAM) bits, register files, embedded dynamic RAM (DRAM) and embedded FPGAs to implement a product specification. In a typical ASIC embodiment selected logic gates are hardwired during chip manufacturing into a required circuit configuration, while in a FPGA embodiment selected logic gates can be programmatically configured into the required circuit configuration during system power-up, or at some other convenient time.
The use of embedded FPGAs is a relatively new development. Due to the inherent programmability of the FPGA, the use of the embedded FPGA is attractive since it provides a mechanism to deal with uncertainty in the logic specification, and it furthermore, permits some degree of customization after a digital logic-containing integrated circuit (chip), such as an ASIC, has been manufactured. However, FPGAs are typically much larger in area, and operate at a significantly slower speed, than equivalent ASIC logic. As a result, the logic designer is presented with the challenge of determining just how to use the mix of components on the chip to best realize the product specification and to also allow for changes in the product definition, while at the same time minimizing design time and cost.
Currently available hardware description languages such as Verilog (Verifying Logic, for which an IEEE standardization process is being finalized as the Verilog 1364-2000 standard), and VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language), another IEEE Standard, are intended for fully specifying logic design. While they do provide unknown constants, they have no direct mechanism for handling “uncertainty” or flexibility in a logic design. Typically, if a logic designer suspects that a logic function may need to be changed, one possible logic function (e.g., a best guess logic function) can be specified and implemented in an FPGA. Subsequently, after the chip is manufactured the embedded FPGA can be programmed to accommodate a change in the design specification. In effect, the logic designer must determine what functions are to be variable, and must select a set of FPGAs for implementation, without any assistance. Further, the decision as to which logic functions are to be variable is not captured in the HDL specification, and must be recorded separately.